| Rev |
Log message |
Author |
Age |
Path |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3041d 08h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3045d 03h |
/ |
| 33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3045d 05h |
/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3045d 05h |
/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3045d 05h |
/ |
| 30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3045d 09h |
/ |
| 29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3046d 01h |
/ |
| 28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3046d 06h |
/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3046d 06h |
/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3046d 06h |
/ |
| 25 |
Fixing compile time warnings. |
dgisselq |
3046d 06h |
/ |
| 24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3052d 04h |
/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3054d 16h |
/ |
| 22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3057d 08h |
/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3107d 15h |
/ |
| 20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3107d 15h |
/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3107d 15h |
/ |
| 18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3111d 05h |
/ |
| 17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3111d 06h |
/ |
| 16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3111d 06h |
/ |
