| Rev |
Log message |
Author |
Age |
Path |
| 53 |
Added a touch of error checking. |
dgisselq |
2988d 18h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2988d 18h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2998d 16h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3007d 19h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3016d 19h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3018d 21h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3018d 21h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3018d 21h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3022d 17h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3022d 17h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3022d 17h |
/ |
| 42 |
Minor changes. |
dgisselq |
3022d 17h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3022d 17h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3024d 03h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3025d 23h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3026d 02h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3026d 21h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3026d 22h |
/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3026d 22h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3030d 17h |
/ |
