URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] - Rev 15

Rev	Log message	Author	Age	Path
15	Fixed LDD, STD	ale500	3609d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/
14	Improved speed and reduced decoder complexity	ale500	3610d 06h	/6809_6309_compatible_core/trunk/rtl/verilog/
13	added missing file with test for cpu	ale500	3623d 08h	/6809_6309_compatible_core/trunk/rtl/verilog/
12	Fixed inc, dec, indirect indexed, mul, shifts, h flag	ale500	3624d 06h	/6809_6309_compatible_core/trunk/rtl/verilog/
11	Fixed inc, dec, clr direct, ext and ind, deca, decb	ale500	3628d 01h	/6809_6309_compatible_core/trunk/rtl/verilog/
10	Fixed several extended and indirect opcodes	ale500	3631d 06h	/6809_6309_compatible_core/trunk/rtl/verilog/
9	Implemented E flag, some minor optimizations	ale500	3805d 06h	/6809_6309_compatible_core/trunk/rtl/verilog/
7	Added SYNC, Fixed EXG	ale500	3806d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/
6	Implemented CWAI. Minor optimizations	ale500	3810d 02h	/6809_6309_compatible_core/trunk/rtl/verilog/
5	EXG/TFR Implemented	ale500	3810d 22h	/6809_6309_compatible_core/trunk/rtl/verilog/
4	Bugfix and enhancements	ale500	3812d 04h	/6809_6309_compatible_core/trunk/rtl/verilog/
2	Initial version	ale500	3814d 02h	/6809_6309_compatible_core/trunk/rtl/verilog/