URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
17	Bugfixes	ale500	3546d 14h	/6809_6309_compatible_core/trunk/rtl/verilog/
16	Fix ABX, TST, implemented new decoder, removed unused logic	ale500	3634d 13h	/6809_6309_compatible_core/trunk/rtl/verilog/
15	Fixed LDD, STD	ale500	3643d 17h	/6809_6309_compatible_core/trunk/rtl/verilog/
14	Improved speed and reduced decoder complexity	ale500	3644d 18h	/6809_6309_compatible_core/trunk/rtl/verilog/
13	added missing file with test for cpu	ale500	3657d 20h	/6809_6309_compatible_core/trunk/rtl/verilog/
12	Fixed inc, dec, indirect indexed, mul, shifts, h flag	ale500	3658d 18h	/6809_6309_compatible_core/trunk/rtl/verilog/
11	Fixed inc, dec, clr direct, ext and ind, deca, decb	ale500	3662d 13h	/6809_6309_compatible_core/trunk/rtl/verilog/
10	Fixed several extended and indirect opcodes	ale500	3665d 18h	/6809_6309_compatible_core/trunk/rtl/verilog/
9	Implemented E flag, some minor optimizations	ale500	3839d 18h	/6809_6309_compatible_core/trunk/rtl/verilog/
7	Added SYNC, Fixed EXG	ale500	3840d 17h	/6809_6309_compatible_core/trunk/rtl/verilog/
6	Implemented CWAI. Minor optimizations	ale500	3844d 14h	/6809_6309_compatible_core/trunk/rtl/verilog/
5	EXG/TFR Implemented	ale500	3845d 10h	/6809_6309_compatible_core/trunk/rtl/verilog/
4	Bugfix and enhancements	ale500	3846d 16h	/6809_6309_compatible_core/trunk/rtl/verilog/
2	Initial version	ale500	3848d 14h	/6809_6309_compatible_core/trunk/rtl/verilog/