URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 109

Rev	Log message	Author	Age	Path
109	add `include "oc8051_defines.v"	simont	7774d 15h	/8051/tags/rel_1/
108	fix some bugs, use oc8051_cache_ram.	simont	7774d 15h	/8051/tags/rel_1/
107	Include instruction cache.	simont	7774d 15h	/8051/tags/rel_1/
106	generic_dpram used	simont	7775d 18h	/8051/tags/rel_1/
105	generic_dpram used	simont	7775d 18h	/8051/tags/rel_1/
104	use generic_dpram	simont	7775d 18h	/8051/tags/rel_1/
103	rename signals	simont	7775d 19h	/8051/tags/rel_1/
102	raname signals.	simont	7775d 19h	/8051/tags/rel_1/
101	initial inport	simont	7775d 22h	/8051/tags/rel_1/
100	use \	simont	7775d 22h	/8051/tags/rel_1/
99	change directory structure	simont	7775d 22h	/8051/tags/rel_1/
98	move to rtl/verilog	simont	7775d 22h	/8051/tags/rel_1/
97	initial inport	simont	7775d 22h	/8051/tags/rel_1/
96	initial import	simont	7775d 22h	/8051/tags/rel_1/
95	updating...	simont	7775d 22h	/8051/tags/rel_1/
94	fix bug.	simont	7775d 22h	/8051/tags/rel_1/
93	OC8051_XILINX_RAM added	simont	7775d 23h	/8051/tags/rel_1/
92	initial inport	simont	7775d 23h	/8051/tags/rel_1/
91	* empty log message *	simont	7775d 23h	/8051/tags/rel_1/
90	change module name.	simont	7780d 16h	/8051/tags/rel_1/