URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 117

Rev	Log message	Author	Age	Path
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7781d 03h	/8051/tags/rel_1/
116	change sfr's interface.	simont	7783d 04h	/8051/tags/rel_1/
115	change uart to meet timing.	simont	7783d 06h	/8051/tags/rel_1/
114	remove t2mod register	simont	7786d 09h	/8051/tags/rel_1/
113	signal prsc_ow added.	simont	7786d 09h	/8051/tags/rel_1/
112	change timers to meet timing specifications (add divider with 12)	simont	7786d 09h	/8051/tags/rel_1/
111	Remove instruction cache and wb_interface	simont	7787d 00h	/8051/tags/rel_1/
110	change adr_i and adr_o length.	simont	7787d 00h	/8051/tags/rel_1/
109	add `include "oc8051_defines.v"	simont	7787d 00h	/8051/tags/rel_1/
108	fix some bugs, use oc8051_cache_ram.	simont	7787d 00h	/8051/tags/rel_1/
107	Include instruction cache.	simont	7787d 00h	/8051/tags/rel_1/
106	generic_dpram used	simont	7788d 03h	/8051/tags/rel_1/
105	generic_dpram used	simont	7788d 03h	/8051/tags/rel_1/
104	use generic_dpram	simont	7788d 03h	/8051/tags/rel_1/
103	rename signals	simont	7788d 04h	/8051/tags/rel_1/
102	raname signals.	simont	7788d 04h	/8051/tags/rel_1/
101	initial inport	simont	7788d 07h	/8051/tags/rel_1/
100	use \	simont	7788d 07h	/8051/tags/rel_1/
99	change directory structure	simont	7788d 07h	/8051/tags/rel_1/
98	move to rtl/verilog	simont	7788d 07h	/8051/tags/rel_1/