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[/] [8051/] [tags/] [rel_1/] - Rev 122

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Rev Log message Author Age Path
122 deifne OC8051_ROM added simont 7782d 06h /8051/tags/rel_1/
121 Change pc add value from 23'h to 16'h simont 7782d 06h /8051/tags/rel_1/
120 defines for pherypherals added simont 7783d 03h /8051/tags/rel_1/
119 remove signal sbuf_txd [12:11] simont 7783d 07h /8051/tags/rel_1/
118 change wr_sft to 2 bit wire. simont 7783d 23h /8051/tags/rel_1/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7784d 00h /8051/tags/rel_1/
116 change sfr's interface. simont 7786d 01h /8051/tags/rel_1/
115 change uart to meet timing. simont 7786d 02h /8051/tags/rel_1/
114 remove t2mod register simont 7789d 05h /8051/tags/rel_1/
113 signal prsc_ow added. simont 7789d 05h /8051/tags/rel_1/
112 change timers to meet timing specifications (add divider with 12) simont 7789d 05h /8051/tags/rel_1/
111 Remove instruction cache and wb_interface simont 7789d 20h /8051/tags/rel_1/
110 change adr_i and adr_o length. simont 7789d 20h /8051/tags/rel_1/
109 add `include "oc8051_defines.v" simont 7789d 20h /8051/tags/rel_1/
108 fix some bugs, use oc8051_cache_ram. simont 7789d 20h /8051/tags/rel_1/
107 Include instruction cache. simont 7789d 20h /8051/tags/rel_1/
106 generic_dpram used simont 7790d 23h /8051/tags/rel_1/
105 generic_dpram used simont 7790d 23h /8051/tags/rel_1/
104 use generic_dpram simont 7790d 23h /8051/tags/rel_1/
103 rename signals simont 7791d 00h /8051/tags/rel_1/

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