URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 126

Rev	Log message	Author	Age	Path
126	define OC8051_XILINX_RAMB added	simont	7777d 02h	/8051/tags/rel_1/
125	update, add prescaler, rclk, tclk.	simont	7777d 02h	/8051/tags/rel_1/
124	add support for external rom from xilinx ramb4	simont	7777d 02h	/8051/tags/rel_1/
123	fiz bug iv pcs operation.	simont	7778d 22h	/8051/tags/rel_1/
122	deifne OC8051_ROM added	simont	7782d 02h	/8051/tags/rel_1/
121	Change pc add value from 23'h to 16'h	simont	7782d 02h	/8051/tags/rel_1/
120	defines for pherypherals added	simont	7783d 00h	/8051/tags/rel_1/
119	remove signal sbuf_txd [12:11]	simont	7783d 03h	/8051/tags/rel_1/
118	change wr_sft to 2 bit wire.	simont	7783d 20h	/8051/tags/rel_1/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7783d 21h	/8051/tags/rel_1/
116	change sfr's interface.	simont	7785d 21h	/8051/tags/rel_1/
115	change uart to meet timing.	simont	7785d 23h	/8051/tags/rel_1/
114	remove t2mod register	simont	7789d 02h	/8051/tags/rel_1/
113	signal prsc_ow added.	simont	7789d 02h	/8051/tags/rel_1/
112	change timers to meet timing specifications (add divider with 12)	simont	7789d 02h	/8051/tags/rel_1/
111	Remove instruction cache and wb_interface	simont	7789d 17h	/8051/tags/rel_1/
110	change adr_i and adr_o length.	simont	7789d 17h	/8051/tags/rel_1/
109	add `include "oc8051_defines.v"	simont	7789d 17h	/8051/tags/rel_1/
108	fix some bugs, use oc8051_cache_ram.	simont	7789d 17h	/8051/tags/rel_1/
107	Include instruction cache.	simont	7789d 17h	/8051/tags/rel_1/