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[/] [8051/] [tags/] [rel_1/] - Rev 139

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Rev Log message Author Age Path
139 add aditional alu destination to solve critical path. simont 7716d 17h /8051/tags/rel_1/
138 Change buffering to save one clock per instruction. simont 7716d 17h /8051/tags/rel_1/
137 change to fit xrom. simont 7716d 22h /8051/tags/rel_1/
136 registering outputs. simont 7716d 22h /8051/tags/rel_1/
135 prepared start of receiving if ren is not active. simont 7722d 22h /8051/tags/rel_1/
134 fix bug in case execution of two data dependent instructions. simont 7722d 22h /8051/tags/rel_1/
133 fix bug in substraction. simont 7723d 00h /8051/tags/rel_1/
132 change branch instruction execution (reduse needed clock periods). simont 7726d 16h /8051/tags/rel_1/
131 prepare programs for new timing. simont 7726d 16h /8051/tags/rel_1/
130 prepared programs for new timing. simont 7726d 16h /8051/tags/rel_1/
129 updated... simont 7726d 16h /8051/tags/rel_1/
128 chance idat_ir to 24 bit wide simont 7735d 23h /8051/tags/rel_1/
127 fix bug (cyc_o and stb_o) simont 7735d 23h /8051/tags/rel_1/
126 define OC8051_XILINX_RAMB added simont 7735d 23h /8051/tags/rel_1/
125 update, add prescaler, rclk, tclk. simont 7735d 23h /8051/tags/rel_1/
124 add support for external rom from xilinx ramb4 simont 7735d 23h /8051/tags/rel_1/
123 fiz bug iv pcs operation. simont 7737d 19h /8051/tags/rel_1/
122 deifne OC8051_ROM added simont 7740d 23h /8051/tags/rel_1/
121 Change pc add value from 23'h to 16'h simont 7740d 23h /8051/tags/rel_1/
120 defines for pherypherals added simont 7741d 20h /8051/tags/rel_1/

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