URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 141

Rev	Log message	Author	Age	Path
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7713d 01h	/8051/tags/rel_1/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7713d 01h	/8051/tags/rel_1/
139	add aditional alu destination to solve critical path.	simont	7713d 19h	/8051/tags/rel_1/
138	Change buffering to save one clock per instruction.	simont	7713d 19h	/8051/tags/rel_1/
137	change to fit xrom.	simont	7714d 00h	/8051/tags/rel_1/
136	registering outputs.	simont	7714d 00h	/8051/tags/rel_1/
135	prepared start of receiving if ren is not active.	simont	7719d 23h	/8051/tags/rel_1/
134	fix bug in case execution of two data dependent instructions.	simont	7719d 23h	/8051/tags/rel_1/
133	fix bug in substraction.	simont	7720d 02h	/8051/tags/rel_1/
132	change branch instruction execution (reduse needed clock periods).	simont	7723d 18h	/8051/tags/rel_1/
131	prepare programs for new timing.	simont	7723d 18h	/8051/tags/rel_1/
130	prepared programs for new timing.	simont	7723d 18h	/8051/tags/rel_1/
129	updated...	simont	7723d 18h	/8051/tags/rel_1/
128	chance idat_ir to 24 bit wide	simont	7733d 01h	/8051/tags/rel_1/
127	fix bug (cyc_o and stb_o)	simont	7733d 01h	/8051/tags/rel_1/
126	define OC8051_XILINX_RAMB added	simont	7733d 01h	/8051/tags/rel_1/
125	update, add prescaler, rclk, tclk.	simont	7733d 01h	/8051/tags/rel_1/
124	add support for external rom from xilinx ramb4	simont	7733d 01h	/8051/tags/rel_1/
123	fiz bug iv pcs operation.	simont	7734d 20h	/8051/tags/rel_1/
122	deifne OC8051_ROM added	simont	7738d 01h	/8051/tags/rel_1/