OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 37

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
37 added signals ack, stb and cyc simont 7970d 17h /8051/tags/rel_1/
36 fix bugs in mode 0 simont 7970d 17h /8051/tags/rel_1/
35 design docunemt simont 7971d 16h /8051/tags/rel_1/
34 specification docunemt simont 7971d 16h /8051/tags/rel_1/
33 fix some bugs simont 7971d 21h /8051/tags/rel_1/
32 overflow repaired simont 7971d 22h /8051/tags/rel_1/
31 fix some bugs simont 7978d 14h /8051/tags/rel_1/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7981d 20h /8051/tags/rel_1/
29 fix some bugs simont 7981d 21h /8051/tags/rel_1/
28 remove syn signal simont 7981d 21h /8051/tags/rel_1/
27 fix some bugs simont 7981d 21h /8051/tags/rel_1/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7981d 23h /8051/tags/rel_1/
25 divider and multiplier pass test markom 7982d 18h /8051/tags/rel_1/
24 intensively tests all instructions markom 7982d 23h /8051/tags/rel_1/
23 mul & div use 4 clocks simont 7983d 13h /8051/tags/rel_1/
22 fix some bugs simont 7983d 13h /8051/tags/rel_1/
21 mul bug fixed markom 7983d 18h /8051/tags/rel_1/
20 multiplier and divider changed so they complete in 4 cycles markom 7983d 21h /8051/tags/rel_1/
19 combinatorial loop removed simont 7984d 13h /8051/tags/rel_1/
18 rst signal added simont 7987d 19h /8051/tags/rel_1/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.