URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5562d 17h	/8051/tags/rel_1/bench/
185		root	5618d 18h	/8051/tags/rel_1/bench/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7747d 16h	/8051/tags/rel_1/bench/
130	prepared programs for new timing.	simont	7764d 15h	/8051/tags/rel_1/bench/
129	updated...	simont	7764d 15h	/8051/tags/rel_1/bench/
125	update, add prescaler, rclk, tclk.	simont	7773d 22h	/8051/tags/rel_1/bench/
124	add support for external rom from xilinx ramb4	simont	7773d 22h	/8051/tags/rel_1/bench/
120	defines for pherypherals added	simont	7779d 20h	/8051/tags/rel_1/bench/
111	Remove instruction cache and wb_interface	simont	7786d 13h	/8051/tags/rel_1/bench/
103	rename signals	simont	7787d 17h	/8051/tags/rel_1/bench/
97	initial inport	simont	7787d 21h	/8051/tags/rel_1/bench/
96	initial import	simont	7787d 21h	/8051/tags/rel_1/bench/
84	remove wb_bus_mon	simont	7866d 18h	/8051/tags/rel_1/bench/
74	add module oc8051_wb_iinterface	simont	7943d 16h	/8051/tags/rel_1/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7947d 19h	/8051/tags/rel_1/bench/
59	add external rom	simont	7954d 13h	/8051/tags/rel_1/bench/
46	prepared header	simont	7971d 15h	/8051/tags/rel_1/bench/
37	added signals ack, stb and cyc	simont	7998d 17h	/8051/tags/rel_1/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8018d 21h	/8051/tags/rel_1/bench/
2	Initial CVS import	simont	8034d 19h	/8051/tags/rel_1/bench/