URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7749d 07h	/8051/tags/rel_1/bench/
111	Remove instruction cache and wb_interface	simont	7756d 01h	/8051/tags/rel_1/bench/
103	rename signals	simont	7757d 05h	/8051/tags/rel_1/bench/
97	initial inport	simont	7757d 08h	/8051/tags/rel_1/bench/
96	initial import	simont	7757d 08h	/8051/tags/rel_1/bench/
84	remove wb_bus_mon	simont	7836d 05h	/8051/tags/rel_1/bench/
74	add module oc8051_wb_iinterface	simont	7913d 03h	/8051/tags/rel_1/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7917d 06h	/8051/tags/rel_1/bench/
59	add external rom	simont	7924d 01h	/8051/tags/rel_1/bench/
46	prepared header	simont	7941d 02h	/8051/tags/rel_1/bench/
37	added signals ack, stb and cyc	simont	7968d 05h	/8051/tags/rel_1/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	7988d 09h	/8051/tags/rel_1/bench/
2	Initial CVS import	simont	8004d 06h	/8051/tags/rel_1/bench/