URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] - Rev 125

Rev	Log message	Author	Age	Path
125	update, add prescaler, rclk, tclk.	simont	7752d 19h	/8051/tags/rel_1/bench/
124	add support for external rom from xilinx ramb4	simont	7752d 19h	/8051/tags/rel_1/bench/
120	defines for pherypherals added	simont	7758d 16h	/8051/tags/rel_1/bench/
111	Remove instruction cache and wb_interface	simont	7765d 09h	/8051/tags/rel_1/bench/
103	rename signals	simont	7766d 14h	/8051/tags/rel_1/bench/
97	initial inport	simont	7766d 17h	/8051/tags/rel_1/bench/
96	initial import	simont	7766d 17h	/8051/tags/rel_1/bench/
84	remove wb_bus_mon	simont	7845d 14h	/8051/tags/rel_1/bench/
74	add module oc8051_wb_iinterface	simont	7922d 12h	/8051/tags/rel_1/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7926d 15h	/8051/tags/rel_1/bench/
59	add external rom	simont	7933d 10h	/8051/tags/rel_1/bench/
46	prepared header	simont	7950d 11h	/8051/tags/rel_1/bench/
37	added signals ack, stb and cyc	simont	7977d 14h	/8051/tags/rel_1/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	7997d 17h	/8051/tags/rel_1/bench/
2	Initial CVS import	simont	8013d 15h	/8051/tags/rel_1/bench/