URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 125

Rev	Log message	Author	Age	Path
125	update, add prescaler, rclk, tclk.	simont	7775d 03h	/8051/tags/rel_1/bench/verilog/
124	add support for external rom from xilinx ramb4	simont	7775d 03h	/8051/tags/rel_1/bench/verilog/
120	defines for pherypherals added	simont	7781d 00h	/8051/tags/rel_1/bench/verilog/
111	Remove instruction cache and wb_interface	simont	7787d 17h	/8051/tags/rel_1/bench/verilog/
103	rename signals	simont	7788d 21h	/8051/tags/rel_1/bench/verilog/
97	initial inport	simont	7789d 01h	/8051/tags/rel_1/bench/verilog/
84	remove wb_bus_mon	simont	7867d 22h	/8051/tags/rel_1/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7944d 20h	/8051/tags/rel_1/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7948d 23h	/8051/tags/rel_1/bench/verilog/
59	add external rom	simont	7955d 18h	/8051/tags/rel_1/bench/verilog/
46	prepared header	simont	7972d 19h	/8051/tags/rel_1/bench/verilog/
37	added signals ack, stb and cyc	simont	7999d 22h	/8051/tags/rel_1/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8020d 01h	/8051/tags/rel_1/bench/verilog/
2	Initial CVS import	simont	8035d 23h	/8051/tags/rel_1/bench/verilog/