URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 185

Rev	Log message	Author	Age	Path
185		root	5590d 02h	/8051/tags/rel_1/bench/verilog/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7719d 00h	/8051/tags/rel_1/bench/verilog/
125	update, add prescaler, rclk, tclk.	simont	7745d 06h	/8051/tags/rel_1/bench/verilog/
124	add support for external rom from xilinx ramb4	simont	7745d 06h	/8051/tags/rel_1/bench/verilog/
120	defines for pherypherals added	simont	7751d 04h	/8051/tags/rel_1/bench/verilog/
111	Remove instruction cache and wb_interface	simont	7757d 21h	/8051/tags/rel_1/bench/verilog/
103	rename signals	simont	7759d 01h	/8051/tags/rel_1/bench/verilog/
97	initial inport	simont	7759d 05h	/8051/tags/rel_1/bench/verilog/
84	remove wb_bus_mon	simont	7838d 02h	/8051/tags/rel_1/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7915d 00h	/8051/tags/rel_1/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7919d 03h	/8051/tags/rel_1/bench/verilog/
59	add external rom	simont	7925d 21h	/8051/tags/rel_1/bench/verilog/
46	prepared header	simont	7942d 23h	/8051/tags/rel_1/bench/verilog/
37	added signals ack, stb and cyc	simont	7970d 01h	/8051/tags/rel_1/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	7990d 05h	/8051/tags/rel_1/bench/verilog/
2	Initial CVS import	simont	8006d 03h	/8051/tags/rel_1/bench/verilog/