URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5527d 12h	/8051/tags/rel_1/bench/verilog/
185		root	5583d 13h	/8051/tags/rel_1/bench/verilog/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7712d 10h	/8051/tags/rel_1/bench/verilog/
125	update, add prescaler, rclk, tclk.	simont	7738d 17h	/8051/tags/rel_1/bench/verilog/
124	add support for external rom from xilinx ramb4	simont	7738d 17h	/8051/tags/rel_1/bench/verilog/
120	defines for pherypherals added	simont	7744d 14h	/8051/tags/rel_1/bench/verilog/
111	Remove instruction cache and wb_interface	simont	7751d 07h	/8051/tags/rel_1/bench/verilog/
103	rename signals	simont	7752d 12h	/8051/tags/rel_1/bench/verilog/
97	initial inport	simont	7752d 15h	/8051/tags/rel_1/bench/verilog/
84	remove wb_bus_mon	simont	7831d 12h	/8051/tags/rel_1/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7908d 10h	/8051/tags/rel_1/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7912d 13h	/8051/tags/rel_1/bench/verilog/
59	add external rom	simont	7919d 08h	/8051/tags/rel_1/bench/verilog/
46	prepared header	simont	7936d 09h	/8051/tags/rel_1/bench/verilog/
37	added signals ack, stb and cyc	simont	7963d 12h	/8051/tags/rel_1/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	7983d 16h	/8051/tags/rel_1/bench/verilog/
2	Initial CVS import	simont	7999d 13h	/8051/tags/rel_1/bench/verilog/