URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 97

Rev	Log message	Author	Age	Path
97	initial inport	simont	7797d 18h	/8051/tags/rel_1/bench/verilog/
84	remove wb_bus_mon	simont	7876d 15h	/8051/tags/rel_1/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7953d 13h	/8051/tags/rel_1/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7957d 16h	/8051/tags/rel_1/bench/verilog/
59	add external rom	simont	7964d 11h	/8051/tags/rel_1/bench/verilog/
46	prepared header	simont	7981d 12h	/8051/tags/rel_1/bench/verilog/
37	added signals ack, stb and cyc	simont	8008d 15h	/8051/tags/rel_1/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8028d 18h	/8051/tags/rel_1/bench/verilog/
2	Initial CVS import	simont	8044d 16h	/8051/tags/rel_1/bench/verilog/