URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 102

Rev	Log message	Author	Age	Path
102	raname signals.	simont	7777d 05h	/8051/tags/rel_1/rtl/
95	updating...	simont	7777d 09h	/8051/tags/rel_1/rtl/
94	fix bug.	simont	7777d 09h	/8051/tags/rel_1/rtl/
93	OC8051_XILINX_RAM added	simont	7777d 09h	/8051/tags/rel_1/rtl/
92	initial inport	simont	7777d 09h	/8051/tags/rel_1/rtl/
90	change module name.	simont	7782d 03h	/8051/tags/rel_1/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7843d 06h	/8051/tags/rel_1/rtl/
88	fix bugs	simont	7848d 06h	/8051/tags/rel_1/rtl/
87	add include oc8051_defines.v	simont	7848d 07h	/8051/tags/rel_1/rtl/
82	replace some modules	simont	7856d 06h	/8051/tags/rel_1/rtl/
81	initial import	simont	7856d 06h	/8051/tags/rel_1/rtl/
80	removing unused modules	simont	7856d 06h	/8051/tags/rel_1/rtl/
78	alu with registered outputs	simont	7916d 06h	/8051/tags/rel_1/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7925d 03h	/8051/tags/rel_1/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7925d 03h	/8051/tags/rel_1/rtl/
75	initial import	simont	7925d 03h	/8051/tags/rel_1/rtl/
73	initial import	simont	7933d 04h	/8051/tags/rel_1/rtl/
72	fix bug in interface to external data ram	simont	7933d 06h	/8051/tags/rel_1/rtl/
67	add parameters for instruction cache	simont	7937d 07h	/8051/tags/rel_1/rtl/
62	fix bugs in instruction interface	simont	7938d 04h	/8051/tags/rel_1/rtl/