URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 112

Rev	Log message	Author	Age	Path
112	change timers to meet timing specifications (add divider with 12)	simont	7798d 21h	/8051/tags/rel_1/rtl/
110	change adr_i and adr_o length.	simont	7799d 12h	/8051/tags/rel_1/rtl/
109	add `include "oc8051_defines.v"	simont	7799d 12h	/8051/tags/rel_1/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7799d 12h	/8051/tags/rel_1/rtl/
107	Include instruction cache.	simont	7799d 12h	/8051/tags/rel_1/rtl/
105	generic_dpram used	simont	7800d 15h	/8051/tags/rel_1/rtl/
104	use generic_dpram	simont	7800d 15h	/8051/tags/rel_1/rtl/
102	raname signals.	simont	7800d 16h	/8051/tags/rel_1/rtl/
95	updating...	simont	7800d 20h	/8051/tags/rel_1/rtl/
94	fix bug.	simont	7800d 20h	/8051/tags/rel_1/rtl/
93	OC8051_XILINX_RAM added	simont	7800d 20h	/8051/tags/rel_1/rtl/
92	initial inport	simont	7800d 20h	/8051/tags/rel_1/rtl/
90	change module name.	simont	7805d 13h	/8051/tags/rel_1/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7866d 17h	/8051/tags/rel_1/rtl/
88	fix bugs	simont	7871d 17h	/8051/tags/rel_1/rtl/
87	add include oc8051_defines.v	simont	7871d 17h	/8051/tags/rel_1/rtl/
82	replace some modules	simont	7879d 17h	/8051/tags/rel_1/rtl/
81	initial import	simont	7879d 17h	/8051/tags/rel_1/rtl/
80	removing unused modules	simont	7879d 17h	/8051/tags/rel_1/rtl/
78	alu with registered outputs	simont	7939d 17h	/8051/tags/rel_1/rtl/