URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 117

Rev	Log message	Author	Age	Path
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7752d 13h	/8051/tags/rel_1/rtl/
116	change sfr's interface.	simont	7754d 14h	/8051/tags/rel_1/rtl/
115	change uart to meet timing.	simont	7754d 16h	/8051/tags/rel_1/rtl/
114	remove t2mod register	simont	7757d 18h	/8051/tags/rel_1/rtl/
113	signal prsc_ow added.	simont	7757d 18h	/8051/tags/rel_1/rtl/
112	change timers to meet timing specifications (add divider with 12)	simont	7757d 18h	/8051/tags/rel_1/rtl/
110	change adr_i and adr_o length.	simont	7758d 10h	/8051/tags/rel_1/rtl/
109	add `include "oc8051_defines.v"	simont	7758d 10h	/8051/tags/rel_1/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7758d 10h	/8051/tags/rel_1/rtl/
107	Include instruction cache.	simont	7758d 10h	/8051/tags/rel_1/rtl/
105	generic_dpram used	simont	7759d 13h	/8051/tags/rel_1/rtl/
104	use generic_dpram	simont	7759d 13h	/8051/tags/rel_1/rtl/
102	raname signals.	simont	7759d 14h	/8051/tags/rel_1/rtl/
95	updating...	simont	7759d 18h	/8051/tags/rel_1/rtl/
94	fix bug.	simont	7759d 18h	/8051/tags/rel_1/rtl/
93	OC8051_XILINX_RAM added	simont	7759d 18h	/8051/tags/rel_1/rtl/
92	initial inport	simont	7759d 18h	/8051/tags/rel_1/rtl/
90	change module name.	simont	7764d 11h	/8051/tags/rel_1/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7825d 15h	/8051/tags/rel_1/rtl/
88	fix bugs	simont	7830d 15h	/8051/tags/rel_1/rtl/