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[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 135

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Rev Log message Author Age Path
135 prepared start of receiving if ren is not active. simont 7738d 14h /8051/tags/rel_1/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7738d 14h /8051/tags/rel_1/rtl/
133 fix bug in substraction. simont 7738d 17h /8051/tags/rel_1/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7742d 08h /8051/tags/rel_1/rtl/
128 chance idat_ir to 24 bit wide simont 7751d 16h /8051/tags/rel_1/rtl/
127 fix bug (cyc_o and stb_o) simont 7751d 16h /8051/tags/rel_1/rtl/
126 define OC8051_XILINX_RAMB added simont 7751d 16h /8051/tags/rel_1/rtl/
123 fiz bug iv pcs operation. simont 7753d 11h /8051/tags/rel_1/rtl/
122 deifne OC8051_ROM added simont 7756d 16h /8051/tags/rel_1/rtl/
121 Change pc add value from 23'h to 16'h simont 7756d 16h /8051/tags/rel_1/rtl/
120 defines for pherypherals added simont 7757d 13h /8051/tags/rel_1/rtl/
119 remove signal sbuf_txd [12:11] simont 7757d 17h /8051/tags/rel_1/rtl/
118 change wr_sft to 2 bit wire. simont 7758d 09h /8051/tags/rel_1/rtl/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7758d 10h /8051/tags/rel_1/rtl/
116 change sfr's interface. simont 7760d 11h /8051/tags/rel_1/rtl/
115 change uart to meet timing. simont 7760d 12h /8051/tags/rel_1/rtl/
114 remove t2mod register simont 7763d 15h /8051/tags/rel_1/rtl/
113 signal prsc_ow added. simont 7763d 15h /8051/tags/rel_1/rtl/
112 change timers to meet timing specifications (add divider with 12) simont 7763d 15h /8051/tags/rel_1/rtl/
110 change adr_i and adr_o length. simont 7764d 06h /8051/tags/rel_1/rtl/

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