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[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 138

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Rev Log message Author Age Path
138 Change buffering to save one clock per instruction. simont 7754d 16h /8051/tags/rel_1/rtl/
137 change to fit xrom. simont 7754d 21h /8051/tags/rel_1/rtl/
136 registering outputs. simont 7754d 21h /8051/tags/rel_1/rtl/
135 prepared start of receiving if ren is not active. simont 7760d 21h /8051/tags/rel_1/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7760d 21h /8051/tags/rel_1/rtl/
133 fix bug in substraction. simont 7760d 23h /8051/tags/rel_1/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7764d 15h /8051/tags/rel_1/rtl/
128 chance idat_ir to 24 bit wide simont 7773d 22h /8051/tags/rel_1/rtl/
127 fix bug (cyc_o and stb_o) simont 7773d 22h /8051/tags/rel_1/rtl/
126 define OC8051_XILINX_RAMB added simont 7773d 22h /8051/tags/rel_1/rtl/
123 fiz bug iv pcs operation. simont 7775d 18h /8051/tags/rel_1/rtl/
122 deifne OC8051_ROM added simont 7778d 22h /8051/tags/rel_1/rtl/
121 Change pc add value from 23'h to 16'h simont 7778d 22h /8051/tags/rel_1/rtl/
120 defines for pherypherals added simont 7779d 19h /8051/tags/rel_1/rtl/
119 remove signal sbuf_txd [12:11] simont 7779d 23h /8051/tags/rel_1/rtl/
118 change wr_sft to 2 bit wire. simont 7780d 16h /8051/tags/rel_1/rtl/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7780d 16h /8051/tags/rel_1/rtl/
116 change sfr's interface. simont 7782d 17h /8051/tags/rel_1/rtl/
115 change uart to meet timing. simont 7782d 19h /8051/tags/rel_1/rtl/
114 remove t2mod register simont 7785d 21h /8051/tags/rel_1/rtl/

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