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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 145

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Rev	Log message	Author	Age	Path
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7752d 21h	/8051/tags/rel_1/rtl/
144	chsnge comp.des to des1	simont	7752d 21h	/8051/tags/rel_1/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7752d 22h	/8051/tags/rel_1/rtl/
142	optimize state machine.	simont	7753d 23h	/8051/tags/rel_1/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7754d 00h	/8051/tags/rel_1/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7754d 00h	/8051/tags/rel_1/rtl/
139	add aditional alu destination to solve critical path.	simont	7754d 18h	/8051/tags/rel_1/rtl/
138	Change buffering to save one clock per instruction.	simont	7754d 18h	/8051/tags/rel_1/rtl/
137	change to fit xrom.	simont	7755d 00h	/8051/tags/rel_1/rtl/
136	registering outputs.	simont	7755d 00h	/8051/tags/rel_1/rtl/
135	prepared start of receiving if ren is not active.	simont	7760d 23h	/8051/tags/rel_1/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7760d 23h	/8051/tags/rel_1/rtl/
133	fix bug in substraction.	simont	7761d 02h	/8051/tags/rel_1/rtl/
132	change branch instruction execution (reduse needed clock periods).	simont	7764d 17h	/8051/tags/rel_1/rtl/
128	chance idat_ir to 24 bit wide	simont	7774d 00h	/8051/tags/rel_1/rtl/
127	fix bug (cyc_o and stb_o)	simont	7774d 00h	/8051/tags/rel_1/rtl/
126	define OC8051_XILINX_RAMB added	simont	7774d 00h	/8051/tags/rel_1/rtl/
123	fiz bug iv pcs operation.	simont	7775d 20h	/8051/tags/rel_1/rtl/
122	deifne OC8051_ROM added	simont	7779d 00h	/8051/tags/rel_1/rtl/
121	Change pc add value from 23'h to 16'h	simont	7779d 00h	/8051/tags/rel_1/rtl/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 145

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