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[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 147

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Rev Log message Author Age Path
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7725d 09h /8051/tags/rel_1/rtl/
146 fix bug in movc intruction. simont 7725d 09h /8051/tags/rel_1/rtl/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7730d 13h /8051/tags/rel_1/rtl/
144 chsnge comp.des to des1 simont 7730d 13h /8051/tags/rel_1/rtl/
143 add wire sub_result, conect it to des_acc and des1. simont 7730d 13h /8051/tags/rel_1/rtl/
142 optimize state machine. simont 7731d 15h /8051/tags/rel_1/rtl/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7731d 16h /8051/tags/rel_1/rtl/
140 cahnge assigment to pc_wait (remove istb_o) simont 7731d 16h /8051/tags/rel_1/rtl/
139 add aditional alu destination to solve critical path. simont 7732d 10h /8051/tags/rel_1/rtl/
138 Change buffering to save one clock per instruction. simont 7732d 10h /8051/tags/rel_1/rtl/
137 change to fit xrom. simont 7732d 15h /8051/tags/rel_1/rtl/
136 registering outputs. simont 7732d 15h /8051/tags/rel_1/rtl/
135 prepared start of receiving if ren is not active. simont 7738d 14h /8051/tags/rel_1/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7738d 14h /8051/tags/rel_1/rtl/
133 fix bug in substraction. simont 7738d 17h /8051/tags/rel_1/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7742d 08h /8051/tags/rel_1/rtl/
128 chance idat_ir to 24 bit wide simont 7751d 16h /8051/tags/rel_1/rtl/
127 fix bug (cyc_o and stb_o) simont 7751d 16h /8051/tags/rel_1/rtl/
126 define OC8051_XILINX_RAMB added simont 7751d 16h /8051/tags/rel_1/rtl/
123 fiz bug iv pcs operation. simont 7753d 11h /8051/tags/rel_1/rtl/

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