URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 20

Rev	Log message	Author	Age	Path
20	multiplier and divider changed so they complete in 4 cycles	markom	8017d 07h	/8051/tags/rel_1/rtl/verilog/
19	combinatorial loop removed	simont	8017d 23h	/8051/tags/rel_1/rtl/verilog/
17	fix some bugs	simont	8021d 05h	/8051/tags/rel_1/rtl/verilog/
16	inputs ram and op2 removed	simont	8021d 05h	/8051/tags/rel_1/rtl/verilog/
15	commbinatorial loop removed	simont	8021d 05h	/8051/tags/rel_1/rtl/verilog/
13	some bug fix	simont	8022d 03h	/8051/tags/rel_1/rtl/verilog/
12	des1_r in alu port list	simont	8022d 03h	/8051/tags/rel_1/rtl/verilog/
11	des2_r removed	simont	8022d 03h	/8051/tags/rel_1/rtl/verilog/
10	% replaced with ^ in uart; some minor improvements	markom	8022d 09h	/8051/tags/rel_1/rtl/verilog/
9	removed unused compare states	markom	8024d 02h	/8051/tags/rel_1/rtl/verilog/
8	some IDS optimizations	markom	8024d 02h	/8051/tags/rel_1/rtl/verilog/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8024d 03h	/8051/tags/rel_1/rtl/verilog/
6	psw combinatorial loop removed	markom	8024d 05h	/8051/tags/rel_1/rtl/verilog/
5	more linter corrections; 2 tests still fail	markom	8024d 06h	/8051/tags/rel_1/rtl/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8024d 07h	/8051/tags/rel_1/rtl/verilog/
2	Initial CVS import	simont	8040d 05h	/8051/tags/rel_1/rtl/verilog/