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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 81

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Rev Log message Author Age Path
81 initial import simont 7872d 04h /8051/tags/rel_1/rtl/verilog/
80 removing unused modules simont 7872d 04h /8051/tags/rel_1/rtl/verilog/
78 alu with registered outputs simont 7932d 04h /8051/tags/rel_1/rtl/verilog/
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7941d 01h /8051/tags/rel_1/rtl/verilog/
76 add module oc8051_sfr, 256 bytes internal ram simont 7941d 01h /8051/tags/rel_1/rtl/verilog/
75 initial import simont 7941d 01h /8051/tags/rel_1/rtl/verilog/
73 initial import simont 7949d 02h /8051/tags/rel_1/rtl/verilog/
72 fix bug in interface to external data ram simont 7949d 04h /8051/tags/rel_1/rtl/verilog/
67 add parameters for instruction cache simont 7953d 05h /8051/tags/rel_1/rtl/verilog/
62 fix bugs in instruction interface simont 7954d 02h /8051/tags/rel_1/rtl/verilog/
54 cahnge interface to instruction rom simont 7960d 00h /8051/tags/rel_1/rtl/verilog/
47 remove unused files simont 7977d 01h /8051/tags/rel_1/rtl/verilog/
46 prepared header simont 7977d 01h /8051/tags/rel_1/rtl/verilog/
45 prepared header simont 7977d 01h /8051/tags/rel_1/rtl/verilog/
44 prepared header simont 7977d 02h /8051/tags/rel_1/rtl/verilog/
41 remove unused files simont 7977d 03h /8051/tags/rel_1/rtl/verilog/
40 added sigals for interacting with external ram simont 7997d 05h /8051/tags/rel_1/rtl/verilog/
38 fix some bugs simont 8004d 03h /8051/tags/rel_1/rtl/verilog/
37 added signals ack, stb and cyc simont 8004d 03h /8051/tags/rel_1/rtl/verilog/
36 fix bugs in mode 0 simont 8004d 03h /8051/tags/rel_1/rtl/verilog/

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