URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [sim/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5509d 03h	/8051/tags/rel_1/sim/
185		root	5565d 04h	/8051/tags/rel_1/sim/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7694d 01h	/8051/tags/rel_1/sim/
106	generic_dpram used	simont	7734d 02h	/8051/tags/rel_1/sim/
101	initial inport	simont	7734d 06h	/8051/tags/rel_1/sim/
100	use \	simont	7734d 06h	/8051/tags/rel_1/sim/
99	change directory structure	simont	7734d 06h	/8051/tags/rel_1/sim/
98	move to rtl/verilog	simont	7734d 06h	/8051/tags/rel_1/sim/
85	prepare bugs	simont	7805d 04h	/8051/tags/rel_1/sim/
83	replace some modules	simont	7813d 03h	/8051/tags/rel_1/sim/
82	replace some modules	simont	7813d 04h	/8051/tags/rel_1/sim/
69	add parameters	simont	7894d 04h	/8051/tags/rel_1/sim/
66	added xrom_test	simont	7895d 01h	/8051/tags/rel_1/sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7895d 01h	/8051/tags/rel_1/sim/
64	signal es_int=1'b0	simont	7895d 01h	/8051/tags/rel_1/sim/
63	initial import	simont	7895d 01h	/8051/tags/rel_1/sim/
58	add external rom testing	simont	7900d 23h	/8051/tags/rel_1/sim/
57	add module oc8051_xrom	simont	7900d 23h	/8051/tags/rel_1/sim/
56	initial CVS input	simont	7900d 23h	/8051/tags/rel_1/sim/
55	added parameter DELAY	simont	7900d 23h	/8051/tags/rel_1/sim/