URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] - Rev 66

Rev	Log message	Author	Age	Path
66	added xrom_test	simont	7936d 12h	/8051/tags/rel_1/sim/rtl_sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7936d 12h	/8051/tags/rel_1/sim/rtl_sim/
64	signal es_int=1'b0	simont	7936d 12h	/8051/tags/rel_1/sim/rtl_sim/
63	initial import	simont	7936d 12h	/8051/tags/rel_1/sim/rtl_sim/
58	add external rom testing	simont	7942d 10h	/8051/tags/rel_1/sim/rtl_sim/
57	add module oc8051_xrom	simont	7942d 10h	/8051/tags/rel_1/sim/rtl_sim/
56	initial CVS input	simont	7942d 10h	/8051/tags/rel_1/sim/rtl_sim/
55	added parameter DELAY	simont	7942d 11h	/8051/tags/rel_1/sim/rtl_sim/
46	prepared header	simont	7959d 12h	/8051/tags/rel_1/sim/rtl_sim/
43	remove unused files	simont	7959d 14h	/8051/tags/rel_1/sim/rtl_sim/
42	* empty log message *	simont	7959d 14h	/8051/tags/rel_1/sim/rtl_sim/
41	remove unused files	simont	7959d 14h	/8051/tags/rel_1/sim/rtl_sim/
37	added signals ack, stb and cyc	simont	7986d 14h	/8051/tags/rel_1/sim/rtl_sim/
19	combinatorial loop removed	simont	8000d 10h	/8051/tags/rel_1/sim/rtl_sim/
18	rst signal added	simont	8003d 16h	/8051/tags/rel_1/sim/rtl_sim/
4	Code repaired to satisfy the linter; testbech fails	markom	8006d 18h	/8051/tags/rel_1/sim/rtl_sim/
2	Initial CVS import	simont	8022d 16h	/8051/tags/rel_1/sim/rtl_sim/