URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 100

Rev	Log message	Author	Age	Path
100	use \	simont	7799d 14h	/8051/tags/rel_12/
99	change directory structure	simont	7799d 14h	/8051/tags/rel_12/
98	move to rtl/verilog	simont	7799d 14h	/8051/tags/rel_12/
97	initial inport	simont	7799d 14h	/8051/tags/rel_12/
96	initial import	simont	7799d 14h	/8051/tags/rel_12/
95	updating...	simont	7799d 14h	/8051/tags/rel_12/
94	fix bug.	simont	7799d 14h	/8051/tags/rel_12/
93	OC8051_XILINX_RAM added	simont	7799d 14h	/8051/tags/rel_12/
92	initial inport	simont	7799d 14h	/8051/tags/rel_12/
91	* empty log message *	simont	7799d 14h	/8051/tags/rel_12/
90	change module name.	simont	7804d 08h	/8051/tags/rel_12/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7865d 11h	/8051/tags/rel_12/
88	fix bugs	simont	7870d 11h	/8051/tags/rel_12/
87	add include oc8051_defines.v	simont	7870d 12h	/8051/tags/rel_12/
86	initial input	simont	7870d 12h	/8051/tags/rel_12/
85	prepare bugs	simont	7870d 12h	/8051/tags/rel_12/
84	remove wb_bus_mon	simont	7878d 11h	/8051/tags/rel_12/
83	replace some modules	simont	7878d 11h	/8051/tags/rel_12/
82	replace some modules	simont	7878d 11h	/8051/tags/rel_12/
81	initial import	simont	7878d 11h	/8051/tags/rel_12/