URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 109

Rev	Log message	Author	Age	Path
109	add `include "oc8051_defines.v"	simont	7793d 02h	/8051/tags/rel_12/
108	fix some bugs, use oc8051_cache_ram.	simont	7793d 02h	/8051/tags/rel_12/
107	Include instruction cache.	simont	7793d 02h	/8051/tags/rel_12/
106	generic_dpram used	simont	7794d 05h	/8051/tags/rel_12/
105	generic_dpram used	simont	7794d 05h	/8051/tags/rel_12/
104	use generic_dpram	simont	7794d 05h	/8051/tags/rel_12/
103	rename signals	simont	7794d 06h	/8051/tags/rel_12/
102	raname signals.	simont	7794d 06h	/8051/tags/rel_12/
101	initial inport	simont	7794d 09h	/8051/tags/rel_12/
100	use \	simont	7794d 09h	/8051/tags/rel_12/
99	change directory structure	simont	7794d 09h	/8051/tags/rel_12/
98	move to rtl/verilog	simont	7794d 09h	/8051/tags/rel_12/
97	initial inport	simont	7794d 09h	/8051/tags/rel_12/
96	initial import	simont	7794d 09h	/8051/tags/rel_12/
95	updating...	simont	7794d 09h	/8051/tags/rel_12/
94	fix bug.	simont	7794d 10h	/8051/tags/rel_12/
93	OC8051_XILINX_RAM added	simont	7794d 10h	/8051/tags/rel_12/
92	initial inport	simont	7794d 10h	/8051/tags/rel_12/
91	* empty log message *	simont	7794d 10h	/8051/tags/rel_12/
90	change module name.	simont	7799d 03h	/8051/tags/rel_12/