URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 115

Rev	Log message	Author	Age	Path
115	change uart to meet timing.	simont	7764d 10h	/8051/tags/rel_12/
114	remove t2mod register	simont	7767d 13h	/8051/tags/rel_12/
113	signal prsc_ow added.	simont	7767d 13h	/8051/tags/rel_12/
112	change timers to meet timing specifications (add divider with 12)	simont	7767d 13h	/8051/tags/rel_12/
111	Remove instruction cache and wb_interface	simont	7768d 04h	/8051/tags/rel_12/
110	change adr_i and adr_o length.	simont	7768d 04h	/8051/tags/rel_12/
109	add `include "oc8051_defines.v"	simont	7768d 04h	/8051/tags/rel_12/
108	fix some bugs, use oc8051_cache_ram.	simont	7768d 04h	/8051/tags/rel_12/
107	Include instruction cache.	simont	7768d 04h	/8051/tags/rel_12/
106	generic_dpram used	simont	7769d 07h	/8051/tags/rel_12/
105	generic_dpram used	simont	7769d 07h	/8051/tags/rel_12/
104	use generic_dpram	simont	7769d 07h	/8051/tags/rel_12/
103	rename signals	simont	7769d 08h	/8051/tags/rel_12/
102	raname signals.	simont	7769d 08h	/8051/tags/rel_12/
101	initial inport	simont	7769d 12h	/8051/tags/rel_12/
100	use \	simont	7769d 12h	/8051/tags/rel_12/
99	change directory structure	simont	7769d 12h	/8051/tags/rel_12/
98	move to rtl/verilog	simont	7769d 12h	/8051/tags/rel_12/
97	initial inport	simont	7769d 12h	/8051/tags/rel_12/
96	initial import	simont	7769d 12h	/8051/tags/rel_12/