URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 136

Rev	Log message	Author	Age	Path
136	registering outputs.	simont	7806d 08h	/8051/tags/rel_12/
135	prepared start of receiving if ren is not active.	simont	7812d 07h	/8051/tags/rel_12/
134	fix bug in case execution of two data dependent instructions.	simont	7812d 07h	/8051/tags/rel_12/
133	fix bug in substraction.	simont	7812d 10h	/8051/tags/rel_12/
132	change branch instruction execution (reduse needed clock periods).	simont	7816d 02h	/8051/tags/rel_12/
131	prepare programs for new timing.	simont	7816d 02h	/8051/tags/rel_12/
130	prepared programs for new timing.	simont	7816d 02h	/8051/tags/rel_12/
129	updated...	simont	7816d 02h	/8051/tags/rel_12/
128	chance idat_ir to 24 bit wide	simont	7825d 09h	/8051/tags/rel_12/
127	fix bug (cyc_o and stb_o)	simont	7825d 09h	/8051/tags/rel_12/
126	define OC8051_XILINX_RAMB added	simont	7825d 09h	/8051/tags/rel_12/
125	update, add prescaler, rclk, tclk.	simont	7825d 09h	/8051/tags/rel_12/
124	add support for external rom from xilinx ramb4	simont	7825d 09h	/8051/tags/rel_12/
123	fiz bug iv pcs operation.	simont	7827d 04h	/8051/tags/rel_12/
122	deifne OC8051_ROM added	simont	7830d 09h	/8051/tags/rel_12/
121	Change pc add value from 23'h to 16'h	simont	7830d 09h	/8051/tags/rel_12/
120	defines for pherypherals added	simont	7831d 06h	/8051/tags/rel_12/
119	remove signal sbuf_txd [12:11]	simont	7831d 10h	/8051/tags/rel_12/
118	change wr_sft to 2 bit wire.	simont	7832d 02h	/8051/tags/rel_12/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7832d 03h	/8051/tags/rel_12/