URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 144

Rev	Log message	Author	Age	Path
144	chsnge comp.des to des1	simont	7771d 03h	/8051/tags/rel_12/
143	add wire sub_result, conect it to des_acc and des1.	simont	7771d 03h	/8051/tags/rel_12/
142	optimize state machine.	simont	7772d 04h	/8051/tags/rel_12/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7772d 06h	/8051/tags/rel_12/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7772d 06h	/8051/tags/rel_12/
139	add aditional alu destination to solve critical path.	simont	7773d 00h	/8051/tags/rel_12/
138	Change buffering to save one clock per instruction.	simont	7773d 00h	/8051/tags/rel_12/
137	change to fit xrom.	simont	7773d 05h	/8051/tags/rel_12/
136	registering outputs.	simont	7773d 05h	/8051/tags/rel_12/
135	prepared start of receiving if ren is not active.	simont	7779d 04h	/8051/tags/rel_12/
134	fix bug in case execution of two data dependent instructions.	simont	7779d 04h	/8051/tags/rel_12/
133	fix bug in substraction.	simont	7779d 07h	/8051/tags/rel_12/
132	change branch instruction execution (reduse needed clock periods).	simont	7782d 22h	/8051/tags/rel_12/
131	prepare programs for new timing.	simont	7782d 22h	/8051/tags/rel_12/
130	prepared programs for new timing.	simont	7782d 22h	/8051/tags/rel_12/
129	updated...	simont	7782d 22h	/8051/tags/rel_12/
128	chance idat_ir to 24 bit wide	simont	7792d 05h	/8051/tags/rel_12/
127	fix bug (cyc_o and stb_o)	simont	7792d 05h	/8051/tags/rel_12/
126	define OC8051_XILINX_RAMB added	simont	7792d 05h	/8051/tags/rel_12/
125	update, add prescaler, rclk, tclk.	simont	7792d 05h	/8051/tags/rel_12/