OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 186

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5509d 21h /8051/tags/rel_12/
185 root 5565d 22h /8051/tags/rel_12/
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7644d 14h /8051/tags/rel_12/
181 Simulation reports added. simont 7644d 14h /8051/tags/rel_12/
179 add /* synopsys xx_case */ to case statments. simont 7644d 15h /8051/tags/rel_12/
178 x replaced with 0. simont 7644d 17h /8051/tags/rel_12/
177 Fix bug in case of writing and reading from same address. simont 7655d 21h /8051/tags/rel_12/
176 ram modules added. simont 7655d 23h /8051/tags/rel_12/
175 initial inport. simont 7655d 23h /8051/tags/rel_12/
174 ram modules added. simont 7655d 23h /8051/tags/rel_12/
173 simualtion `ifdef added simont 7655d 23h /8051/tags/rel_12/
172 BIST signals added. simont 7658d 22h /8051/tags/rel_12/
171 fix bug in DA operation. simont 7666d 19h /8051/tags/rel_12/
170 removing unused files. simont 7666d 20h /8051/tags/rel_12/
169 remove unused files. simont 7666d 20h /8051/tags/rel_12/
168 modify program list. simont 7666d 20h /8051/tags/rel_12/
167 add readmem for ea. simont 7670d 02h /8051/tags/rel_12/
166 Change test monitor from ports to external data memory. simont 7670d 19h /8051/tags/rel_12/
165 remove dumpvars. simont 7670d 23h /8051/tags/rel_12/
164 initial inport. simont 7671d 00h /8051/tags/rel_12/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.