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[/] [8051/] [tags/] [rel_12/] - Rev 39

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39 added signals ack, stb and cyc simont 8010d 11h /8051/tags/rel_12/
38 fix some bugs simont 8010d 11h /8051/tags/rel_12/
37 added signals ack, stb and cyc simont 8010d 11h /8051/tags/rel_12/
36 fix bugs in mode 0 simont 8010d 11h /8051/tags/rel_12/
35 design docunemt simont 8011d 09h /8051/tags/rel_12/
34 specification docunemt simont 8011d 09h /8051/tags/rel_12/
33 fix some bugs simont 8011d 15h /8051/tags/rel_12/
32 overflow repaired simont 8011d 15h /8051/tags/rel_12/
31 fix some bugs simont 8018d 08h /8051/tags/rel_12/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8021d 14h /8051/tags/rel_12/
29 fix some bugs simont 8021d 15h /8051/tags/rel_12/
28 remove syn signal simont 8021d 15h /8051/tags/rel_12/
27 fix some bugs simont 8021d 15h /8051/tags/rel_12/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8021d 17h /8051/tags/rel_12/
25 divider and multiplier pass test markom 8022d 11h /8051/tags/rel_12/
24 intensively tests all instructions markom 8022d 16h /8051/tags/rel_12/
23 mul & div use 4 clocks simont 8023d 07h /8051/tags/rel_12/
22 fix some bugs simont 8023d 07h /8051/tags/rel_12/
21 mul bug fixed markom 8023d 12h /8051/tags/rel_12/
20 multiplier and divider changed so they complete in 4 cycles markom 8023d 14h /8051/tags/rel_12/

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