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[/] [8051/] [tags/] [rel_12/] [bench/] [verilog/] - Rev 186

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Rev Log message Author Age Path
186 root 5531d 08h /8051/tags/rel_12/bench/verilog/
185 root 5587d 09h /8051/tags/rel_12/bench/verilog/
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7666d 01h /8051/tags/rel_12/bench/verilog/
167 add readmem for ea. simont 7691d 13h /8051/tags/rel_12/bench/verilog/
166 Change test monitor from ports to external data memory. simont 7692d 06h /8051/tags/rel_12/bench/verilog/
165 remove dumpvars. simont 7692d 10h /8051/tags/rel_12/bench/verilog/
157 change data output. simont 7692d 12h /8051/tags/rel_12/bench/verilog/
156 add FREQ paremeter. simont 7692d 12h /8051/tags/rel_12/bench/verilog/
125 update, add prescaler, rclk, tclk. simont 7742d 13h /8051/tags/rel_12/bench/verilog/
124 add support for external rom from xilinx ramb4 simont 7742d 13h /8051/tags/rel_12/bench/verilog/
120 defines for pherypherals added simont 7748d 11h /8051/tags/rel_12/bench/verilog/
111 Remove instruction cache and wb_interface simont 7755d 04h /8051/tags/rel_12/bench/verilog/
103 rename signals simont 7756d 08h /8051/tags/rel_12/bench/verilog/
97 initial inport simont 7756d 12h /8051/tags/rel_12/bench/verilog/
84 remove wb_bus_mon simont 7835d 09h /8051/tags/rel_12/bench/verilog/
74 add module oc8051_wb_iinterface simont 7912d 07h /8051/tags/rel_12/bench/verilog/
68 add instruction cache and DELAY parameters for external ram, rom simont 7916d 10h /8051/tags/rel_12/bench/verilog/
59 add external rom simont 7923d 04h /8051/tags/rel_12/bench/verilog/
46 prepared header simont 7940d 06h /8051/tags/rel_12/bench/verilog/
37 added signals ack, stb and cyc simont 7967d 08h /8051/tags/rel_12/bench/verilog/

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