URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [bench/] [verilog/] - Rev 68

Rev	Log message	Author	Age	Path
68	add instruction cache and DELAY parameters for external ram, rom	simont	7959d 12h	/8051/tags/rel_12/bench/verilog/
59	add external rom	simont	7966d 07h	/8051/tags/rel_12/bench/verilog/
46	prepared header	simont	7983d 08h	/8051/tags/rel_12/bench/verilog/
37	added signals ack, stb and cyc	simont	8010d 10h	/8051/tags/rel_12/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 14h	/8051/tags/rel_12/bench/verilog/
2	Initial CVS import	simont	8046d 12h	/8051/tags/rel_12/bench/verilog/