URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [bench/] [verilog/] - Rev 84

Rev	Log message	Author	Age	Path
84	remove wb_bus_mon	simont	7914d 01h	/8051/tags/rel_12/bench/verilog/
74	add module oc8051_wb_iinterface	simont	7990d 22h	/8051/tags/rel_12/bench/verilog/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7995d 01h	/8051/tags/rel_12/bench/verilog/
59	add external rom	simont	8001d 20h	/8051/tags/rel_12/bench/verilog/
46	prepared header	simont	8018d 22h	/8051/tags/rel_12/bench/verilog/
37	added signals ack, stb and cyc	simont	8046d 00h	/8051/tags/rel_12/bench/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8066d 04h	/8051/tags/rel_12/bench/verilog/
2	Initial CVS import	simont	8082d 02h	/8051/tags/rel_12/bench/verilog/