URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 121

Rev	Log message	Author	Age	Path
121	Change pc add value from 23'h to 16'h	simont	7798d 04h	/8051/tags/rel_12/rtl/
120	defines for pherypherals added	simont	7799d 02h	/8051/tags/rel_12/rtl/
119	remove signal sbuf_txd [12:11]	simont	7799d 05h	/8051/tags/rel_12/rtl/
118	change wr_sft to 2 bit wire.	simont	7799d 22h	/8051/tags/rel_12/rtl/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7799d 23h	/8051/tags/rel_12/rtl/
116	change sfr's interface.	simont	7801d 23h	/8051/tags/rel_12/rtl/
115	change uart to meet timing.	simont	7802d 01h	/8051/tags/rel_12/rtl/
114	remove t2mod register	simont	7805d 04h	/8051/tags/rel_12/rtl/
113	signal prsc_ow added.	simont	7805d 04h	/8051/tags/rel_12/rtl/
112	change timers to meet timing specifications (add divider with 12)	simont	7805d 04h	/8051/tags/rel_12/rtl/
110	change adr_i and adr_o length.	simont	7805d 19h	/8051/tags/rel_12/rtl/
109	add `include "oc8051_defines.v"	simont	7805d 19h	/8051/tags/rel_12/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7805d 19h	/8051/tags/rel_12/rtl/
107	Include instruction cache.	simont	7805d 19h	/8051/tags/rel_12/rtl/
105	generic_dpram used	simont	7806d 22h	/8051/tags/rel_12/rtl/
104	use generic_dpram	simont	7806d 22h	/8051/tags/rel_12/rtl/
102	raname signals.	simont	7806d 23h	/8051/tags/rel_12/rtl/
95	updating...	simont	7807d 03h	/8051/tags/rel_12/rtl/
94	fix bug.	simont	7807d 03h	/8051/tags/rel_12/rtl/
93	OC8051_XILINX_RAM added	simont	7807d 03h	/8051/tags/rel_12/rtl/