OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 145

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
145 fix bug in case of sequence of inc dptr instrucitons. simont 7756d 06h /8051/tags/rel_12/rtl/
144 chsnge comp.des to des1 simont 7756d 06h /8051/tags/rel_12/rtl/
143 add wire sub_result, conect it to des_acc and des1. simont 7756d 06h /8051/tags/rel_12/rtl/
142 optimize state machine. simont 7757d 07h /8051/tags/rel_12/rtl/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7757d 09h /8051/tags/rel_12/rtl/
140 cahnge assigment to pc_wait (remove istb_o) simont 7757d 09h /8051/tags/rel_12/rtl/
139 add aditional alu destination to solve critical path. simont 7758d 03h /8051/tags/rel_12/rtl/
138 Change buffering to save one clock per instruction. simont 7758d 03h /8051/tags/rel_12/rtl/
137 change to fit xrom. simont 7758d 08h /8051/tags/rel_12/rtl/
136 registering outputs. simont 7758d 08h /8051/tags/rel_12/rtl/
135 prepared start of receiving if ren is not active. simont 7764d 07h /8051/tags/rel_12/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7764d 07h /8051/tags/rel_12/rtl/
133 fix bug in substraction. simont 7764d 10h /8051/tags/rel_12/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7768d 01h /8051/tags/rel_12/rtl/
128 chance idat_ir to 24 bit wide simont 7777d 08h /8051/tags/rel_12/rtl/
127 fix bug (cyc_o and stb_o) simont 7777d 08h /8051/tags/rel_12/rtl/
126 define OC8051_XILINX_RAMB added simont 7777d 09h /8051/tags/rel_12/rtl/
123 fiz bug iv pcs operation. simont 7779d 04h /8051/tags/rel_12/rtl/
122 deifne OC8051_ROM added simont 7782d 08h /8051/tags/rel_12/rtl/
121 Change pc add value from 23'h to 16'h simont 7782d 08h /8051/tags/rel_12/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.