URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 172

Rev	Log message	Author	Age	Path
172	BIST signals added.	simont	7677d 05h	/8051/tags/rel_12/rtl/
171	fix bug in DA operation.	simont	7685d 03h	/8051/tags/rel_12/rtl/
158	fix bug.	simont	7689d 08h	/8051/tags/rel_12/rtl/
153	`ifdef added.	simont	7691d 02h	/8051/tags/rel_12/rtl/
152	sub_result output added.	simont	7691d 02h	/8051/tags/rel_12/rtl/
151	remove pc_r register.	simont	7691d 02h	/8051/tags/rel_12/rtl/
150	fix some bugs.	simont	7691d 02h	/8051/tags/rel_12/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7691d 02h	/8051/tags/rel_12/rtl/
148	include "8051_defines" added.	simont	7691d 03h	/8051/tags/rel_12/rtl/
146	fix bug in movc intruction.	simont	7713d 03h	/8051/tags/rel_12/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7718d 07h	/8051/tags/rel_12/rtl/
144	chsnge comp.des to des1	simont	7718d 07h	/8051/tags/rel_12/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7718d 07h	/8051/tags/rel_12/rtl/
142	optimize state machine.	simont	7719d 08h	/8051/tags/rel_12/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7719d 10h	/8051/tags/rel_12/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7719d 10h	/8051/tags/rel_12/rtl/
139	add aditional alu destination to solve critical path.	simont	7720d 04h	/8051/tags/rel_12/rtl/
138	Change buffering to save one clock per instruction.	simont	7720d 04h	/8051/tags/rel_12/rtl/
137	change to fit xrom.	simont	7720d 09h	/8051/tags/rel_12/rtl/
136	registering outputs.	simont	7720d 09h	/8051/tags/rel_12/rtl/