URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 179

Rev	Log message	Author	Age	Path
179	add /* synopsys xx_case */ to case statments.	simont	7662d 23h	/8051/tags/rel_12/rtl/
178	x replaced with 0.	simont	7663d 01h	/8051/tags/rel_12/rtl/
177	Fix bug in case of writing and reading from same address.	simont	7674d 04h	/8051/tags/rel_12/rtl/
175	initial inport.	simont	7674d 06h	/8051/tags/rel_12/rtl/
174	ram modules added.	simont	7674d 06h	/8051/tags/rel_12/rtl/
173	simualtion `ifdef added	simont	7674d 06h	/8051/tags/rel_12/rtl/
172	BIST signals added.	simont	7677d 06h	/8051/tags/rel_12/rtl/
171	fix bug in DA operation.	simont	7685d 03h	/8051/tags/rel_12/rtl/
158	fix bug.	simont	7689d 09h	/8051/tags/rel_12/rtl/
153	`ifdef added.	simont	7691d 03h	/8051/tags/rel_12/rtl/
152	sub_result output added.	simont	7691d 03h	/8051/tags/rel_12/rtl/
151	remove pc_r register.	simont	7691d 03h	/8051/tags/rel_12/rtl/
150	fix some bugs.	simont	7691d 03h	/8051/tags/rel_12/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7691d 03h	/8051/tags/rel_12/rtl/
148	include "8051_defines" added.	simont	7691d 03h	/8051/tags/rel_12/rtl/
146	fix bug in movc intruction.	simont	7713d 03h	/8051/tags/rel_12/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7718d 07h	/8051/tags/rel_12/rtl/
144	chsnge comp.des to des1	simont	7718d 07h	/8051/tags/rel_12/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7718d 07h	/8051/tags/rel_12/rtl/
142	optimize state machine.	simont	7719d 09h	/8051/tags/rel_12/rtl/