URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 25

Rev	Log message	Author	Age	Path
25	divider and multiplier pass test	markom	7983d 04h	/8051/tags/rel_12/rtl/
23	mul & div use 4 clocks	simont	7984d 00h	/8051/tags/rel_12/rtl/
22	fix some bugs	simont	7984d 00h	/8051/tags/rel_12/rtl/
21	mul bug fixed	markom	7984d 05h	/8051/tags/rel_12/rtl/
20	multiplier and divider changed so they complete in 4 cycles	markom	7984d 07h	/8051/tags/rel_12/rtl/
19	combinatorial loop removed	simont	7985d 00h	/8051/tags/rel_12/rtl/
17	fix some bugs	simont	7988d 05h	/8051/tags/rel_12/rtl/
16	inputs ram and op2 removed	simont	7988d 05h	/8051/tags/rel_12/rtl/
15	commbinatorial loop removed	simont	7988d 05h	/8051/tags/rel_12/rtl/
13	some bug fix	simont	7989d 03h	/8051/tags/rel_12/rtl/
12	des1_r in alu port list	simont	7989d 03h	/8051/tags/rel_12/rtl/
11	des2_r removed	simont	7989d 04h	/8051/tags/rel_12/rtl/
10	% replaced with ^ in uart; some minor improvements	markom	7989d 10h	/8051/tags/rel_12/rtl/
9	removed unused compare states	markom	7991d 02h	/8051/tags/rel_12/rtl/
8	some IDS optimizations	markom	7991d 03h	/8051/tags/rel_12/rtl/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	7991d 04h	/8051/tags/rel_12/rtl/
6	psw combinatorial loop removed	markom	7991d 06h	/8051/tags/rel_12/rtl/
5	more linter corrections; 2 tests still fail	markom	7991d 06h	/8051/tags/rel_12/rtl/
4	Code repaired to satisfy the linter; testbech fails	markom	7991d 08h	/8051/tags/rel_12/rtl/
2	Initial CVS import	simont	8007d 06h	/8051/tags/rel_12/rtl/