URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 46

Rev	Log message	Author	Age	Path
46	prepared header	simont	7943d 21h	/8051/tags/rel_12/rtl/
45	prepared header	simont	7943d 22h	/8051/tags/rel_12/rtl/
44	prepared header	simont	7943d 22h	/8051/tags/rel_12/rtl/
41	remove unused files	simont	7943d 23h	/8051/tags/rel_12/rtl/
40	added sigals for interacting with external ram	simont	7964d 01h	/8051/tags/rel_12/rtl/
38	fix some bugs	simont	7970d 23h	/8051/tags/rel_12/rtl/
37	added signals ack, stb and cyc	simont	7971d 00h	/8051/tags/rel_12/rtl/
36	fix bugs in mode 0	simont	7971d 00h	/8051/tags/rel_12/rtl/
32	overflow repaired	simont	7972d 04h	/8051/tags/rel_12/rtl/
31	fix some bugs	simont	7978d 20h	/8051/tags/rel_12/rtl/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7982d 03h	/8051/tags/rel_12/rtl/
29	fix some bugs	simont	7982d 03h	/8051/tags/rel_12/rtl/
28	remove syn signal	simont	7982d 04h	/8051/tags/rel_12/rtl/
27	fix some bugs	simont	7982d 04h	/8051/tags/rel_12/rtl/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7982d 06h	/8051/tags/rel_12/rtl/
25	divider and multiplier pass test	markom	7983d 00h	/8051/tags/rel_12/rtl/
23	mul & div use 4 clocks	simont	7983d 19h	/8051/tags/rel_12/rtl/
22	fix some bugs	simont	7983d 20h	/8051/tags/rel_12/rtl/
21	mul bug fixed	markom	7984d 01h	/8051/tags/rel_12/rtl/
20	multiplier and divider changed so they complete in 4 cycles	markom	7984d 03h	/8051/tags/rel_12/rtl/