OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 73

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 initial import simont 7921d 17h /8051/tags/rel_12/rtl/
72 fix bug in interface to external data ram simont 7921d 19h /8051/tags/rel_12/rtl/
67 add parameters for instruction cache simont 7925d 20h /8051/tags/rel_12/rtl/
62 fix bugs in instruction interface simont 7926d 17h /8051/tags/rel_12/rtl/
54 cahnge interface to instruction rom simont 7932d 15h /8051/tags/rel_12/rtl/
47 remove unused files simont 7949d 16h /8051/tags/rel_12/rtl/
46 prepared header simont 7949d 16h /8051/tags/rel_12/rtl/
45 prepared header simont 7949d 17h /8051/tags/rel_12/rtl/
44 prepared header simont 7949d 17h /8051/tags/rel_12/rtl/
41 remove unused files simont 7949d 18h /8051/tags/rel_12/rtl/
40 added sigals for interacting with external ram simont 7969d 20h /8051/tags/rel_12/rtl/
38 fix some bugs simont 7976d 18h /8051/tags/rel_12/rtl/
37 added signals ack, stb and cyc simont 7976d 19h /8051/tags/rel_12/rtl/
36 fix bugs in mode 0 simont 7976d 19h /8051/tags/rel_12/rtl/
32 overflow repaired simont 7977d 23h /8051/tags/rel_12/rtl/
31 fix some bugs simont 7984d 15h /8051/tags/rel_12/rtl/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7987d 22h /8051/tags/rel_12/rtl/
29 fix some bugs simont 7987d 22h /8051/tags/rel_12/rtl/
28 remove syn signal simont 7987d 23h /8051/tags/rel_12/rtl/
27 fix some bugs simont 7987d 23h /8051/tags/rel_12/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.