URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 82

Rev	Log message	Author	Age	Path
82	replace some modules	simont	7867d 03h	/8051/tags/rel_12/rtl/
81	initial import	simont	7867d 03h	/8051/tags/rel_12/rtl/
80	removing unused modules	simont	7867d 03h	/8051/tags/rel_12/rtl/
78	alu with registered outputs	simont	7927d 03h	/8051/tags/rel_12/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7936d 00h	/8051/tags/rel_12/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7936d 00h	/8051/tags/rel_12/rtl/
75	initial import	simont	7936d 00h	/8051/tags/rel_12/rtl/
73	initial import	simont	7944d 01h	/8051/tags/rel_12/rtl/
72	fix bug in interface to external data ram	simont	7944d 03h	/8051/tags/rel_12/rtl/
67	add parameters for instruction cache	simont	7948d 04h	/8051/tags/rel_12/rtl/
62	fix bugs in instruction interface	simont	7949d 01h	/8051/tags/rel_12/rtl/
54	cahnge interface to instruction rom	simont	7954d 23h	/8051/tags/rel_12/rtl/
47	remove unused files	simont	7972d 00h	/8051/tags/rel_12/rtl/
46	prepared header	simont	7972d 00h	/8051/tags/rel_12/rtl/
45	prepared header	simont	7972d 00h	/8051/tags/rel_12/rtl/
44	prepared header	simont	7972d 01h	/8051/tags/rel_12/rtl/
41	remove unused files	simont	7972d 02h	/8051/tags/rel_12/rtl/
40	added sigals for interacting with external ram	simont	7992d 04h	/8051/tags/rel_12/rtl/
38	fix some bugs	simont	7999d 02h	/8051/tags/rel_12/rtl/
37	added signals ack, stb and cyc	simont	7999d 02h	/8051/tags/rel_12/rtl/