URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 104

Rev	Log message	Author	Age	Path
104	use generic_dpram	simont	7771d 19h	/8051/tags/rel_12/rtl/verilog/
102	raname signals.	simont	7771d 20h	/8051/tags/rel_12/rtl/verilog/
95	updating...	simont	7772d 00h	/8051/tags/rel_12/rtl/verilog/
94	fix bug.	simont	7772d 00h	/8051/tags/rel_12/rtl/verilog/
93	OC8051_XILINX_RAM added	simont	7772d 00h	/8051/tags/rel_12/rtl/verilog/
92	initial inport	simont	7772d 00h	/8051/tags/rel_12/rtl/verilog/
90	change module name.	simont	7776d 17h	/8051/tags/rel_12/rtl/verilog/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7837d 21h	/8051/tags/rel_12/rtl/verilog/
88	fix bugs	simont	7842d 21h	/8051/tags/rel_12/rtl/verilog/
87	add include oc8051_defines.v	simont	7842d 21h	/8051/tags/rel_12/rtl/verilog/
82	replace some modules	simont	7850d 21h	/8051/tags/rel_12/rtl/verilog/
81	initial import	simont	7850d 21h	/8051/tags/rel_12/rtl/verilog/
80	removing unused modules	simont	7850d 21h	/8051/tags/rel_12/rtl/verilog/
78	alu with registered outputs	simont	7910d 21h	/8051/tags/rel_12/rtl/verilog/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7919d 18h	/8051/tags/rel_12/rtl/verilog/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7919d 18h	/8051/tags/rel_12/rtl/verilog/
75	initial import	simont	7919d 18h	/8051/tags/rel_12/rtl/verilog/
73	initial import	simont	7927d 18h	/8051/tags/rel_12/rtl/verilog/
72	fix bug in interface to external data ram	simont	7927d 20h	/8051/tags/rel_12/rtl/verilog/
67	add parameters for instruction cache	simont	7931d 21h	/8051/tags/rel_12/rtl/verilog/