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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 120

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Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7791d 07h	/8051/tags/rel_12/rtl/verilog/
119	remove signal sbuf_txd [12:11]	simont	7791d 11h	/8051/tags/rel_12/rtl/verilog/
118	change wr_sft to 2 bit wire.	simont	7792d 03h	/8051/tags/rel_12/rtl/verilog/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7792d 04h	/8051/tags/rel_12/rtl/verilog/
116	change sfr's interface.	simont	7794d 05h	/8051/tags/rel_12/rtl/verilog/
115	change uart to meet timing.	simont	7794d 06h	/8051/tags/rel_12/rtl/verilog/
114	remove t2mod register	simont	7797d 09h	/8051/tags/rel_12/rtl/verilog/
113	signal prsc_ow added.	simont	7797d 09h	/8051/tags/rel_12/rtl/verilog/
112	change timers to meet timing specifications (add divider with 12)	simont	7797d 09h	/8051/tags/rel_12/rtl/verilog/
110	change adr_i and adr_o length.	simont	7798d 01h	/8051/tags/rel_12/rtl/verilog/
109	add `include "oc8051_defines.v"	simont	7798d 01h	/8051/tags/rel_12/rtl/verilog/
108	fix some bugs, use oc8051_cache_ram.	simont	7798d 01h	/8051/tags/rel_12/rtl/verilog/
107	Include instruction cache.	simont	7798d 01h	/8051/tags/rel_12/rtl/verilog/
105	generic_dpram used	simont	7799d 04h	/8051/tags/rel_12/rtl/verilog/
104	use generic_dpram	simont	7799d 04h	/8051/tags/rel_12/rtl/verilog/
102	raname signals.	simont	7799d 05h	/8051/tags/rel_12/rtl/verilog/
95	updating...	simont	7799d 08h	/8051/tags/rel_12/rtl/verilog/
94	fix bug.	simont	7799d 08h	/8051/tags/rel_12/rtl/verilog/
93	OC8051_XILINX_RAM added	simont	7799d 09h	/8051/tags/rel_12/rtl/verilog/
92	initial inport	simont	7799d 09h	/8051/tags/rel_12/rtl/verilog/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 120

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