URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 16

Rev	Log message	Author	Age	Path
16	inputs ram and op2 removed	simont	8034d 22h	/8051/tags/rel_12/rtl/verilog/
15	commbinatorial loop removed	simont	8034d 22h	/8051/tags/rel_12/rtl/verilog/
13	some bug fix	simont	8035d 20h	/8051/tags/rel_12/rtl/verilog/
12	des1_r in alu port list	simont	8035d 20h	/8051/tags/rel_12/rtl/verilog/
11	des2_r removed	simont	8035d 20h	/8051/tags/rel_12/rtl/verilog/
10	% replaced with ^ in uart; some minor improvements	markom	8036d 02h	/8051/tags/rel_12/rtl/verilog/
9	removed unused compare states	markom	8037d 19h	/8051/tags/rel_12/rtl/verilog/
8	some IDS optimizations	markom	8037d 19h	/8051/tags/rel_12/rtl/verilog/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8037d 20h	/8051/tags/rel_12/rtl/verilog/
6	psw combinatorial loop removed	markom	8037d 22h	/8051/tags/rel_12/rtl/verilog/
5	more linter corrections; 2 tests still fail	markom	8037d 22h	/8051/tags/rel_12/rtl/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8038d 00h	/8051/tags/rel_12/rtl/verilog/
2	Initial CVS import	simont	8053d 22h	/8051/tags/rel_12/rtl/verilog/